15.04.24 | Vollzeit | Freiburg im Breisgau | JobLeads GmbH | 100.000 € - 125.000 € Functional group, with Engineers contributing across the full ASIC flow. Experience or knowledge in verification or back-end is a huge plus! Key skills for this position - Experience in RTL design for complex ASIC projects. - Completion of multiple successful tape-outs. - Experience with Verilog
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