24.05.25 | Vollzeit | Neuried (Bayern) | JobLeads GmbH | 60.000 € - 80.000 € With SystemVerilog assertions 4. Understanding of ARM-AMBA protocols, Verilog constructs to debug RTL issues and C+ constructs to debug TLM models 5. Working experience with Cadence simulation/regression tools (Xcelium, Specman-elite, SimVision, vManager) 6. Experience on requirement-based verification for ISO
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