28.04.24 | Vollzeit | Grünwald | RTL 2 - BistroDas RTL2 - Bistro ist seit 20 Jahren eine besondere, feine, kleine Kantine mit einem täglich wechselnden á la carte Speiseangebot. Unser kreatives Küchenteam kombiniert verschiedene einheimische, mediterrane, asiatische & orientalische Einflüsse in Ihrem täglichen Angebot. Anstellungsart Vollzeit A
Später ansehen30.04.24 | Vollzeit | München | JobLeads GmbH | 125.000 € - 150.000 € Qualifications You Will Perform block level P&R, and integration from early RTL to final tapeout Work closely with logic designers on block level timing closure Work closely with custom cell development Improve capacity and scalability of our full chip design flows Develop scripts to enhance current physical
Später ansehen15.04.24 | Vollzeit | München | JobLeads GmbH | 100.000 € - 125.000 € And hardware setups Design and debug emulation system hardware Set up and maintain software tool flows supporting RTL synthesis to an FPGA. Define and execute experiments to support product design Debug and troubleshoot lab setup issues Qualifications Bachelor/Masters in Electrical or Computer Engineering
Später ansehen30.03.24 | Vollzeit | München | JobLeads GmbH | 100.000 € - 125.000 € ASIC Engineer Location San Jose, CA Duration 6 Months Minimum Required Skills ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal (Cadence Tool for formal verification) Description Should have 2-5 years of experience in FPGA/ASIC Development Build RTL
Später ansehen30.03.24 | Vollzeit | München | JobLeads GmbH | 100.000 € - 125.000 € Contribute to microarchitecture, RTL design, synthesis, and timing closure. Qualifications We would love to hear from you if 8+ years of professional design experience. - Hands-on ASIC front-end design, ideally in design services environments. - Micro-architecture at module/sub-system/chip-level. - Digital
Später ansehen30.03.24 | Vollzeit | München | JobLeads GmbH | 100.000 € - 125.000 € Through all phases of ASIC execution. - Ensure designs meets product performance requirements by performing related tasks. - Contribute to microarchitecture, RTL design, synthesis, and timing closure. Qualifications We would love to hear from you if 8+ years of professional design experience. - Hands
Später ansehen30.03.24 | Vollzeit | München | JobLeads GmbH | 100.000 € - 125.000 € Verification Duties • Verification plan creation for various blocks • Develop the SoC/Subsystem Test case suite in various stages like RTL,GLS releases. • Integrate System Verilog, OVM Test bench components like Scoreboard, Monitors and Bus Function Models. • Develop System Level Scenario’s for full Chip
Später ansehen28.03.24 | Vollzeit | München | JobLeads GmbH | 100.000 € - 125.000 € Individual contributor Requirements - secret government clearance within last 5 years - good knowledge of EDA tools and scripting - BSEE with 8 years of experience or MSEE with 5 years’ experience in static timing & RTL Design - Must be a very good team player with a very good oral, written and interpersonal
Später ansehen14.03.24 | Vollzeit | München | JobLeads GmbH | 100.000 € - 125.000 € Responsible for executing verification plan according to the product specification and verification requirements defined by product architects and deliver zero defect IPs. - Responsible for architecting, developing, debugging, and running UVM based verification environment for RTL simulation. - Define
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